VHDL Programming

Basic Overview

VHDL is a hardware description language (HDL) used to describe digital logic so it can be simulated and then synthesized into hardware, such as an FPGA logic. In the hardware design flow, simulation is used to verify correctness before implementation, and synthesis converts the HDL description into a gate-level netlist.

Unlike normal software programming, VHDL does not primarily describe a sequence of instructions for a CPU to execute. Instead, it describes hardware structure and behavior: signals, combinational logic, sequential logic, registers, state machines, and module interconnections. RPI’s recent hardware design slide deck explicitly frames HDLs this way and lists SystemVerilog and VHDL 2008 as the two leading HDLs.

What VHDL Is Used For

VHDL is commonly used to:

• describe combinational logic
• describe sequential logic
• build finite-state machines
• create hierarchical digital systems
• simulate circuits before hardware implementation
• synthesize designs for FPGA targets

A typical VHDL workflow is:

1. write the design
2. simulate it with a testbench
3. synthesize it
4. implement it on the target FPGA or hardware platform

Core Structure of a VHDL File